PIC18F26K80-I/SO【PDF 56/351 页】MCU PIC 64KB FLASH 28SOIC

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2010-2012 Microchip Technology Inc.

DS39977F-page 149

PIC18F66K80 FAMILY

10.1

INTCON Registers

The INTCON registers are readable and writable

registers that contain various enable, priority and flag

bits.

Note:

Interrupt flag bits are set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit. User software should

ensure the appropriate interrupt flag bits

are clear prior to enabling an interrupt.

This feature allows for software polling.

REGISTER 10-1:

INTCON: INTERRUPT CONTROL REGISTER

R/W-0

R/W-x

GIE/GIEH

PEIE/GIEL

TMR0IE

INT0IE

RBIE(2)

TMR0IF

INT0IF

RBIF(1)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

GIE/GIEH:

Global Interrupt Enable bit

When IPEN = 0:

= Enables all unmasked interrupts

= Disables all interrupts

When IPEN = 1:

= Enables all high-priority interrupts

= Disables all interrupts

bit 6

PEIE/GIEL:

Peripheral Interrupt Enable bit

When IPEN = 0:

= Enables all unmasked peripheral interrupts

= Disables all peripheral interrupts

When IPEN = 1:

= Enables all low-priority peripheral interrupts

= Disables all low-priority peripheral interrupts

bit 5

TMR0IE:

TMR0 Overflow Interrupt Enable bit

= Enables the TMR0 overflow interrupt

= Disables the TMR0 overflow interrupt

bit 4

INT0IE:

INT0 External Interrupt Enable bit

= Enables the INT0 external interrupt

= Disables the INT0 external interrupt

bit 3

RBIE:

RB Port Change Interrupt Enable bit(2)

= Enables the RB port change interrupt

= Disables the RB port change interrupt

bit 2

TMR0IF:

TMR0 Overflow Interrupt Flag bit

= TMR0 register has overflowed (must be cleared in software)

= TMR0 register has not overflowed

bit 1

INT0IF:

INT0 External Interrupt Flag bit

= The INT0 external interrupt occurred (must be cleared in software)

= The INT0 external interrupt did not occur

bit 0

RBIF:

RB Port Change Interrupt Flag bit(1)

= At least one of the RB<7:4> pins changed state (must be cleared in software)

= None of the RB<7:4> pins have changed state

Note 1:

A mismatch condition will continue to set this bit. To end the mismatch condition and allow the bit to be

cleared, read PORTB and wait one additional instruction cycle.

Each pin on PORTB for interrupt-on-change is individually enabled and disabled in the IOCB register. By

default, all pins are disabled.

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